1. Field of the Invention
The present invention relates generally to speech coding and more specifically to an improvement to the detection of errors in coded speech signals.
2. Description of the Related Art
In order to allow receive sites to detect errors in a transmitted bit sequence, it is the usual practice to introduce, at the transmit site, redundant bits such as cyclic redundant check (CRC) bits to information bits. However, the error detector at the receive site may fail to detect errors if the received bit sequence contains too many errors to handle. It is known that, for a given number of redundant error check bits, the number of errors which go unnoticed by the error detector tends to increase with an increase in the number of information bits protected by the error check bits. Specifically, in an error detection encoder for coded speech signals, an input bit sequence is separated into a first sequence of higher priorities and a second sequence of lower priorities (i.e., error unprotected bits). The first sequence is used to derive a CRC sequence which is concatenated to the first sequence so that the first sequence is a sequence of error protected bits. The sequence of error protected bits is concatenated to the sequence of error unprotected bits to form an output bit sequence for further processing for transmission.
However, since the number of CRC check bits of the known error detection encoder is fixed and invariable and the operating performance of the error detection decoder at the receive site is determined by the number of CRC check bits contained in a received signal, the error detection decoder cannot increase detectable errors. In addition, if a substantial number of unprotected lower priority bits are consecutively affected by noise during transmission, the quality of the received signal may deteriorate unacceptably.
It is therefore an object of the present invention to provide an error detection encoder for producing a bit sequence that allows affected bits to be detected at a receive site without using an increased number of redundant error check bits.
According to the present invention, an error detection encoder is provided which comprises separation circuitry for separating an input signal into a first sequence of error protected bits and a second sequence of error unprotected bits, and calculation circuitry for producing an error check sequence from the first sequence and concatenating the error check sequence to the first sequence to produce a third sequence. A multiplexer is provided for segmenting the third sequence into a plurality of first blocks and segmenting the second sequence into a plurality of second blocks corresponding to the first blocks and multiplexing each of the first blocks with a corresponding one of the second blocks to produce a fourth sequence in which the first and the second blocks are arranged in an alternating order.
In one embodiment of the present invention, the input signal is a coded speech signal, and the first sequence comprises higher significant bits of the coded speech signal and the second sequence comprises lower significant bits of the coded speech signal.
Preferably, the separation circuitry is arranged to additionally separate a fifth sequence of error unprotected bits from the input signal in addition to the first and second sequences and this fifth sequence is concatenated to the fourth sequence. In addition, the second sequence has such a length that, if it were corrupted during transmission and were decoded by a speech decoder at a receive site, no unacceptable noise would be produced.